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Energy Efficient Computing

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Electronic System Level Design: The search for new methodologies and tools suitable to the new Electronic System Level approach to hardware design. I have been working on new technologies related to SystemC and the ArchC architecture description language in order to aid the design on high levels of abstraction. Internet of Things IoT : Advances in information technology, sensors, wireless communication and embedded processors are enabling the deployment of low cost and low power sensors and actuators that will connect our world in a way never seen before.

Interoperability is a key aspect in this scenario. I am interested in investigating technologies to enable seamless device integration as well as techniques to combine data from multiple sensors to improve user experience.


  • Declarative Programming, Sasbachwalden 1991: PHOENIX Seminar and Workshop on Declarative Programming, Sasbachwalden, Black Forest, Germany, 18–22 November 1991.
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  • Electronic System Level Design – three years on.

System's Security: We are a small research group from the University of Campinas with topics that range through areas such as network security, compilers, computer architecture, assembly languages, software memory and code flow corruption. Control Flow Integrity, Memory protection through hardware enhancements, and System Design Exploitation are amongs the topics we are interested in. Read more Code Optimization, Dynamic Compilation: Creating new optimizations, or adapting some existent technique, in order to generate efficient code and several aspects of dynamic code generation and its application in virtual machines.

I have recently worked on topics like: region formation techniques, evaluating dynamic compilation overhead, and bynary translation based techniques to handle security issues, like program shepperding.

ESL Design and Verification

Selected Publications Adaptive global power optimization for Web servers. Full Text Empirical and analytical approaches for web server power modeling. Data center power and performance optimization through global selection of P-states and utilization rates.